Design Verification Engineer (San Jose) Job at LeadStack Inc., San Jose, CA

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  • LeadStack Inc.
  • San Jose, CA

Job Description

Overview

Job Title: DV Engineer

Duration: 06 Months

Location: San Jose, CA 95134

Pay Range: $65 - $75/hour on W2

Description: 3+ year experience in Austin; 5+ year experience in SJC (mostly working remotely with design and DV team in Austin, so needs to work independently)

Base pay range

$65.00/hr - $75.00/hr

Responsibilities

  • Developing and Implementing Verification Plans
  • Writing Test cases with both constrained-random and directed test cases to thoroughly exercise the design
  • Analyzing Simulation Results to identify and debug functional failures, working closely with design engineers
  • Debugging; identifying and resolving functional failures in the design, often in collaboration with design team
  • Collaborating with Teams: working with design, Cmodel and GC-level DV to ensure design quality and efficient verification closure

Qualifications

  • SystemVerilog: proficient in SystemVerilog for developing testbenches and test cases
  • UVM: solid understanding and practical experience with UVM (Universal Verification Methodology)
  • Debugging: strong debugging skills to identify and resolve functional failures
  • Verification Planning: experience in developing and executing verification test plans
  • Collaboration: Ability to work effectively in a team environment
  • Communication: strong verbal and written communication skills
  • Problem-Solving: Ability to independently solve complex problems and proposed solutions

Job Details

  • Seniority level: Mid-Senior level
  • Employment type: Contract
  • Job function: Manufacturing and Engineering
  • Industries: Appliances, Electrical, and Electronics Manufacturing and Semiconductor Manufacturing
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Job Tags

Contract work, Part time, Remote work,

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