Job Description

Responsibilities

• Developing and Implementing Verification Plans



• Building Testbenches using Universal Verification Methodology (UVM)



• Writing Test cases with both constrained-random and directed test cases to thoroughly exercise the design



• Analyzing Simulation Results to identify and debug functional failures, working closely with design engineers



• Debugging; identifying and resolving functional failures in the design, often in collaboration with design team



• Collaborating with Teams: working with design, Cmodel and GC-level DV to ensure design quality and efficient verification closure

Qualifications

• SystemVerilog: proficient in SystemVerilog for developing testbenches and test cases



• UVM: solid understanding and practical experience with UVM (Universal Verification Methodology)



• Debugging: strong debugging skills to identify and resolve functional failures



• Verification Planning: experience in developing and executing verification test plans



• Collaboration: Ability to work effectively in a team environment



• Communication: strong verbal and written communication skills



• Problem-Solving: Ability to independently solve complex problems and proposed solutions

Seniority level

• Associate

Employment type

• Contract

Job function

• Manufacturing

Industries

• Information Services and Semiconductor Manufacturing

Job Tags

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